CV8986
General Description
The CV8986 device is a high quality, multi-format analog video and audio convert with HD transmitter . The CV8986 device supports YPbPr video signals up to 1080p60 resolution and RGB graphics signals from VGA to UXGA resolution.
The device contains a 24 Bits audio ADC, So CV8986 can accept three format audio signal: Digital audio S/PDIF and I2S, analog stereo Line in.
The Cv8986 embeds 32-bit ARM Cortex™-M0 processor with speed up to 48mhz. It can realize single chip system without external control module
Features
Analog Video Front-end
Three 10-bit ADCs sampling up to 170Mhz
Flexible input multiplexers to support YPbPr and VGA
Consumer Electronics Control(CEC ) version 1.3
Automatic format detection
Automatic calibration
Support 480i/p, 576i/p, 720p25/30/50/60, 1080i50/60, 1080p24/25/30/50/60
Support RGB graphics from VGA to UXGA
Support Macrovision
Analog audio Front-end
Advance Multi-bit ΔΣ Architecture
24-bit Conversion
Supports Audio Sample Rates Up to 108Khz
Low-Latency Digital Filter
Digital audio interface
Four I2S inputs with sample rate of 32~192Khz
S/PDIF interface supporting PCM,Dolby Digital, DTS digital audio at up to 192Khz frame rate
Compatible with IEC 60958 and IEC 61937
HD Transmitter
HD 1.3/DVI 1.0 compliant transmitter up to 170Mhz, supporting 1080p and UXGA.
Monitor detection

Pin Diagram

Function Block Diagram

Function Description
Video Analog Front-end (AFE)
The Video Analog Front-end (AFE) provides three input channels for R, G, and B. Each channel includes an Input Multiplexer, a Clamp and Offset DAC, a Programmable Low-pass Filter, and a high quality 10-bit ADC with Programmable Gain Amplifier. In addition, there is a PLL to generate sampling clocks for ADCs, Sync Slicers to handle SOG signals.
Video Processing
Time Base Corrector
The Time Base Corrector (TBC) is designed to provide stable clock and video data for HD output.
Color Processing (CP)
Brightness, Contrast, Saturation controller
444 to 422 Decimation
Color Space Converters (CSC) :RGB to YCbCr and YCbCr to RGB
Auto Phase Detection (APD)
Auto Phase Detection is a module used to search for the phases that can generate the best display quality. The desired phases, in general, can generate sharp and stable images, if the input image meets certain criteria during phase detection period. APD is an automatic algorithm that can be enabled or disabled by software. It can be applied to both VGA and Component inputs.
Auto Position Calibration (APC)
Auto Position Calibration detects the active picture area of input video signal and adjusts the output timing so that the final picture can fit to the display properly.
Auto Gain Calibration (AGC)
Slight mismatch of analog input channels including offset and gain may impact the picture quality. The device has been well designed to keep the mismatches in acceptable range (<0.5 dB). It is still important to calibrate these mismatches in some cases to achieve the most accurate picture. To help manufactures to finish this process in low cost and short time, an Auto Gain Calibration mechanism is designed in the device. This mechanism will automatically measure the digitized signal levels through AGC module, calculate the correct values.
Audio Processing
The CV8986 can accept analog video signal Line-in and digital audio signal S/PDIF, I2S inputs.
Audio Analog Front-end (AFE)
Stereo, 24-Bit Advanced Multi-Bit ΔΣ Architecture analog to digital converter.
Low-Latency Digital Filter.
High-Pass Filter to Remove DC Offsets
S/PDIF
The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for multi-channel (IEC 61937) formats. The audio data capture logic forms the audio data into packets in accordance with the HD specification. The S/PDIF input supports audio sampling rates from 32 to 192 kHz.
Pin Description
| PIN | Signal Name | Type | Dir | Description |
| 1 | AVSS | Ground | P/G | Audio ADC Ground |
| 2 | ARIN | Analog | Input | Line Input for Left Channel. |
| 3 | ALIN | Analog | Input | Line Input for Right Channel. |
| 4 | AV33 | Power | 3.3V power supply | |
| 5 | SPDIF | Schmitt | Input | S/PDIF Audio Input. |
| 6 | DV18 | Power | P/G | Digital power 1.8V |
| 7 | HPD | Schmit 5-V tolerant | Inpput | Hot Plug Detect Input. |
| 8 | DDC_SDA | Schmitt Open-drain 5-V tolerant | Input/Output | DDC I2C Bus Data. |
| 9 | DDC_SCL | Schmitt 5-V tolerant | Input/Output | DDC I2C Bus Clock. |
| 10 | PC0 | Input | 0: VGA IN; 1:Ypbpr IN | |
| 11 | NRST | Reset, connect 100nF cap to Gnd | ||
| 12 | VDD33 | Power | P/G | Power 3.3V |
| 13 | VDD33 | Power | P/G | Power 3.3V |
| 14 | AVSS | Ground | P/G | Analog Ground |
| 15 | REXT | Analog | Input | Voltage Swing Adjust.A resistor is connected from this signal to GROUND.This resistor determines the amplitude of the voltage swing. |
| 16 | AVSS | Power | P/G | Analog Ground |
| 17 | TXCN | TMDS | Output | TMDS output clock pair. |
| 18 | TXCP | TMDS | Output | |
| 19 | AV18H | Power | P/G | HD TX 1.8V Power |
| 20 | TX0N | TMDS | Output | TMDS ouptut data0 pairs. |
| 21 | TX0P | TMDS | Output | |
| 22 | AVSS | Ground | P/G | Analog Ground |
| 23 | TX1N | TMDS | Output | TMDS ouptut data1 pairs. |
| 24 | TX1P | TMDS | Output | |
| 25 | AV18H | Power | P/G | HD TX 1.8V Power |
| 26 | TX2N | TMDS | Output | TMDS ouptut data1 pairs. |
| 27 | TX2P | TMDS | Output | |
| 28 | AVSS | Ground | P/G | Analog Ground |
| 29 | DV33 | Power | P/G | Ground |
| 30 | XTI | Crystal Input. | ||
| 31 | XTO | Crystal Output. | ||
| 32 | DVSS | Ground | P/G | Ground |
| 33 | SCL | Schmitt | Input/Output | Serial Port Data Clock |
| 34 | SDA | Schmitt Open drain | Input/Output | Serial Port Data I/O |
| 35 | DVDD18 | Power | P/G | Digital Power 1.8V |
| 36 | PA11 | GPIO | ||
| 37 | PA12 | Audio select,0: L/R IN;1:SPDIF IN | ||
| 38 | SWDIO | ISP DATA | ||
| 39 | SWCLK | ISP CLK | ||
| 40 | HS_IN | Schmitt 5-V tolerant | Input | Horizontal Sync Input |
| 41 | VS_IN | Schmit 5-V tolerant | Input | Vertical Sync Input |
| 42 | DV33 | Power | P/G | Digital IO power 3.3V |
| 43 | VGADP | VGA INPUT valid status | ||
| 44 | HDDP | HD HPD STATUS | ||
| 45 | GND | |||
| 46 | VGA_SCL | Schmitt | Input/Output | Serial Port Data Clock |
| 47 | VGA_SDA | Schmit Open drain | Input/Output | Serial Port Data I/O |
| 48 | BIN | Analog | Input | Analog Input for Blue Channel |
| 49 | AVSS | Ground | P/G | Analog Ground |
| 50 | SOG | Analog | Input | Sync-on-Green Input |
| 51 | GIN | Analog | Input | Analog Input for Green Channel |
| 52 | AV18 | Power | P/G | Analog 1.8V |
| 53 | AVSS | Ground | P/G | Analog Ground |
| 54 | AV33 | Power | P/G | Analog 3.3V |
| 55 | RIN | Analog | Input | Analog Input for Red Channel |
| 56 | AVSS | Power | P/G | Analog Ground |
| 57 | EP1 | Ground | P/G | EPAD,Connect to Ground |
Packaging

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